Vertical conduction MOSgated devices are well known. By MOSgated device is meant a MOSFET, IGBT or the like. By a vertical conduction device is meant a device in which at least a portion of the current conduction path through the die is perpendicular to the plane of the die. By die is meant a single die or chip which is singulated from a wafer in which all die within the wafer are simultaneously processed before singulation. The terms die, wafer and chip may be interchangeably used.
FIG. 1 shows a known type of vertical conduction MOSFET, using a trench type technology. FIG. 1 is a cross-section through a MOSFET die and shows one cell of a device. A plurality of identical such cells which are laterally disposed relative to one another are conventionally employed. These cells may be parallel stripes, or closed cells of circular, rectangular, square, hexagonal or any other polygonal topology and may appear identical in a cross-sectional view. The device of FIG. 1 has its drain on the bottom of the die and the source and gate on the opposite surface.
In FIG. 1, the wafer or die has an N+ substrate 20 of monocrystalline silicon (float zone, for example) which has a top epitaxially grown N type silicon layer, which includes drift region 21. A P type base implant and diffusion into the epitaxial layer forms the P base region 22, and an N type implant and diffusion forms the N+ source region layer 23. Spaced trenches 24 and 25 (or spaced, or enclosed cells) are formed in the top of the wafer. A silicon dioxide or other insulation liner has a thick bottom section 30 and a thin vertical gate section 31 which receive a conductive polysilicon gate electrode 32. A top oxide segment 33 completes an insulated enclosure for gate polysilicon 32. A source electrode 40 is then deposited atop the wafer or chip and fills trench 24 to short the N+ source 23 to the P base, thereby to disable the parasitic bipolar transistor formed by regions 21, 22 and 23. A conductive drain electrode 41 is conventionally formed on the bottom of the die.
In operation, the application of a gate turn-on potential to gate 32 relative to source 40 will invert the concentration at the surface of P base 22 which lines oxide 31, thus permitting the vertical flow of majority carriers from drain 41 to source 40.
It would be very desirable for many applications to reduce the capacitance between the gate and drain and thus the charge Qgd and Q switch and to reduce the on resistance RDSON and gate resistance of the MOSgated device die of FIG. 1. It would also be desirable to provide a MOSgated die structure which can be packaged in a variety of housings and can be copacked in a package with other die with reduced package resistance, minimal stray inductance, and good heat sinking capability.
Top drain MOSgated devices are broadly shown, in copending application Ser. No. 11/042,993, filed Mar. 4, 2005, in the name of Daniel M. Kinzer, entitled TOP DRAIN MOSFET (IR-2471) and assigned to the assignee of this coinvention. Such devices have reversed source and drain electrodes as compared to those of a conventional MOSFET. Thus, both the drain structure and gate structure are formed in the top of the chip, and the source is at the bottom of the chip. Spaced vertical gate trenches are formed into the top of the die or wafer. A base or channel invertible region is disposed adjacent the trench wall and is burried beneath an upper drift region. A further trench or cell disposed between the gate trenches permits the formation of a conductive region at its bottom to short the buried P base to the N+ substrate.
This novel reversal of functions produces a significant improvement in R*Qsw and R*A over current technology (60% and 26% respectively). It further enables a four times reduction in gate resistance and enables multiple packaging options for the copackaging of die.
More specifically, the structure permits a reduction of the drain to gate overlap and the use of a thicker oxide between gate and drain, thus producing a reduced Qgd and Qsw. The design also allows the use of higher cell density and the elimination of the JFET effect both reduce RDSON. Finally, the design permits the reduction of gate resistance.